Low Power Techniques : Contemporary Strategies - I

Most of the SoC designs for mobile domain(by Mobile Domain, I mean the devices being used in SmartPhones, tablets, laptops, or any gadget which can be carried from one place to another easily) require it to consume low power while performing operations at the same time.

This article discusses the various contemporary techniques (in brief) employed by the Design companies in coming up with such complex SoCs. Before we proceed any further, I would like to differentiate between two terms which are often used interchangeably in the industry these days. They are : Low Power and Power Aware

There is a difference in the two terms which I mentioned above. Be known that “Low Power is not the same as Power Aware.”

Difference between Low Power and Power Aware Techniques

Low Power (in the context of these devices) means that the device will consume low power owing to the way it is implemented. One example for this would be the use of High Threshold (High Vth) MOS transistors in the design which has lesser leakage and performs slower than the Low Vth transistors which are leaky.

Power Aware, on the other hand, implies that the SoC or device itself is intelligent enough to shut down or turn-off the units which are not required while performing a particular operation or the device knows when to operate at a lower frequency or in a low power consuming mode/state.

Contemporary SoCs are a mingled version of Power Aware as well as Low Power Techniques to have an optimum performance and power consumption at the same time. Due to excessive power consumption by these small devices, a new parameter has emerged as a metric for SoCs. It is Performance per Watt or in Industry Lingo it is Perf/Watt. Know that this number will be different for different types of tests/benchmarks we run on the design. Generally the worst case Perf/Watt should be reported.

So here I go on listing and summarizing the techniques that are being used.

I leave it to you to categorize the technique as low power or power aware. J

The first and simplest to understand is MTCMOS

1.      MTCMOS (Multi – Threshold CMOS)

Fig 1.  Types of MOS Transistors with different Vt

 As mentioned above, this technique is highly useful in reducing leakage power. Every company has its own standard cell library and a standard library is provided by “The Foundry” as well. This library (the one provided by the foundary) contains transistors with varying thresholds or different Vth’s. Since low Vth implies(these cells are termed as LVT cells; LVT standing for Low Vth) higher leakage but high speed, we tend to use them in timing critical paths (What is a timing critical path??) or in other words, the path which has the largest delay (arising from flops, combo logic) in it. For all other paths or in between logic, we use the cells with medium Vth(SVT for Small Vth) or high Vth(HVT for High Vth) which has lower performance but are highly tolerant to leakage power. In fig 1b., the solid dashed line in the gate is used to depict that it is a high threshold device. The Vth of the transistor is changed by varying the oxide (SiO2) thickness in the MOS transistor and hence the solid line for showing thick oxide layer in fig 1b. 

For details you can visit this article again :  Basics of MOS Devices 

2.      Multiple Supply Voltages

Fig 2. A SoC with Multiple Voltage Islands

Kindly note that above figure is arbitrarily drawn and bears no resemblance to any existing SoC. 

For a long time the industry has been dreaded by the dynamic power consumption which is a strong function of the operating voltage, frequency and load capacitance, given by the relation :

P_dyn = C_LVDD²f

Note that in above equation I have not considered the switching factor.

As per above equation if we reduce the operating voltage by 2 by keeping all the other things constant, the dynamic power would be reduced by a factor of 4. This simple approach is used in coming up with SoCs which have different voltage islands in it. The different parts of the SoC operate on different voltages, and of course on different frequencies. As an example the audio unit in any SoC can operate at lower frequency than the display unit and hence we can use different voltages for these two types of IP’s. Such scenario is depicted in figure above.

I’ll talk about more about the remaining techniques in a follow - up article.

Till then, “It is not the end but a start of new era of revolution”.

Quiz #1 Switching Activity Calculation for N input gates

This is one of the “many to follow” quizzes and it is taken from Digital Integrated Circuits by Jan M. Rabaey, et al. (One of the best books in the world for learning about the Digital Integrated Circuits). Soon we will have real life circuits(Which are heavily used in the semiconductor industry) to analyze in the quiz section. 

Switching Activity

 We all know that the dynamic power dissipation in is given as :

P(dynamic) = α_0->1C_LV_DD²f

Here the factor α_0->1 is termed as switching activity (or the transition activity). The transition activity is a strong function of logic function (the logic operation being performed by any of the digital gates like AND, OR, NAND, etc). For gates implemented using static CMOS technology, this factor is a multiplication of the two probabilities (The subscript 0->1 is there as for static CMOS gates  power is only consumed when the output switches from 0 to 1 and not other way round as we have a direct path from supply to the output when output transitions from 0 to 1. More to follow on this in the device section):

P₀: The probability that the output will be “0” in present cycle (or for the matter in any cycle)

P₁: The probability that the output will be “1” in the next cycle (or for the matter subsequent cycle of the cycle under consideration).

So α_0->1 = P₀*P₁ or in other words

α_0->1 = P₀*(1-P₀)

If we assume that the inputs to the N input gates are not related to each other (which is a practical consideration) and are distributed uniformly over time, then the switching activity is given as :

α_0->1 = (N₀/2^N)* (N₁/2^N)= N₀(2^N – N₀)/2^2N

N₀: It is the number of “0” entries in the output column of truth table for that gate

N₁: It is the number of “1” entries in the output column of the truth table for the same gate

Now for the problem; suppose we have N input XOR, NOR and NAND gates. Assuming the above assumptions to be valid what should be the switching activity for the above gates? What will be the probability if we replace the N input gates with an inverter?

                                                                   Fig 1. N input NAND Gate

The answers to above questions are simple and easier to find with the above mentioned details.

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