VLSI/ASIC Job Opportunity in Bangalore

Hi All,

We are looking for candidates interested in VLSI/ASIC having relevant work experience.

Location : Bangalore

The Job Description (JD) is below.

Please mail your resume/cv @ socasicdesign@gmail.com with following subject line : [JD Applying for]_[Years of Experience]_experience

JD :

Design Engineer
Required skills and knowledge :
1. BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE
2. Knowledgeable in System Verilog RTL coding, PERL, Timing
3. Strong Knowledge on the IP development flow is must
4. FPGA Prototyping of the IP is a plus
5. Domain expertise in Networking protocols/Interface protocols like PCIe, USB, SATA
6. Working knowledge in Multi-clock domains and Power domains is an added advantage
7. Good Communication skills with ability and desire to work as a good team player

Verification Engineer
Required skills and knowledge :
1. BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE
2. Design and develop testbenches using HVLs like System Verilog, Specman, etc
3. Deep expertise in Verification Methodologies like OVM, UVM, VMM
4. Should have experience in creating verification environment and test plans
5. Domain expertise in Networking protocols/Interface protocols like PCIe, USB, SATA / SoC Verification is a plus
6. Familiarity with Scripting languages
7. Good communication skills with ability and desire to work as a good team player

Verification | System Verilog | Universal Verification Methodology - I

Over the last few months, I have been working on verification of SoCs using System Verilog/Universal Verification Methodology (or popularly known as SV/UVM in the VLSI Industry). I thought that I will create a list of sites, links to the important documents from various sources which I have used to develop my skill set in the said area. 

Also, I will try to list the interview questions which are highly useful and generally asked by most of the VLSI Companies hiring for SV/UVM/Verification skill set. 

One of my friends has done a very good job of compiling a library to learn about SV/UVM on his site Verification Guide . One of the best thing about this site is that you can compile the code and run it on EDA Playground, a free online tool provider for running simulation/synthesis and many other utilities. EDA Playground is now a part of Doulos.

Verification guide provides you with lots of examples and also to test these examples by making the changes to the code on EDA Playground.

Do let me know your feedback, if you found the examples to be useful.

Before I close on this article, one important remark I would like to make is that knowing the language alone does not close the case. Language is just a tool to solve a problem. It is the problem solving ability that matters. :)

Please do look out for this section as there are many articles coming up in this space(Along with generally asked interview questions)

Closing with the lines of  John Johnson, “First, solve the problem. Then, write the code.” 

Till next post!!!