Resets - I

Why do we need RESETS?

Resets in any SoC (or for the matter in any complicated chip) are required to put it in a known or sane state. An example of resetting is when our mobile phone hangs we generally shut it down so that it comes back to normal state (Shutting down is equivalent to resetting it). Similarly resets are required so that any SoC can be brought back to a default state.

                                                           Fig 1. D type Flip Flop with Reset Pin
During the design phase we apply reset while simulating the design, the resets are used to ensure that the initial state of system is known and then we force them into the other states for the purpose of simulation. Also they ensure that the hardware is in a known state as circuits have no inbuilt method for self- initializing them. For a real hardware system or board, when we power up the system we reset everything so that we know which register contains what before we start any other operation on it. A typical modern day SoC contains hundreds of register and knowing the state of each register is almost impossible unless we reset them in the start and then put them into operational states.

Another use case of reset is in watchdog counter circuits. I will talk about watchdog circuits in a later post, but for now I can tell that watchdog circuits are used to ensure that the circuit does not enter into a deadlock state. For e.g assume that two processes are running in parallel on a system. Let us call them Process A and Process B. Process A wants to use a system resource and it issues a request for using it and at the same time Process B wants to use the same resource and it also issues the same request (resource here refers to a hardware resource). Since both the requests are issued at the same time, each process will assume that the resource is busy and being used by another process and this will go on indefinitely with neither process using the resource. In order to get out of such a situation we have a counter circuit which times out after a certain number of clock cycles and then either of process can use the resource.

Above was one example of a deadlock, there are other examples as well, I will discuss about them in some future post. For now let us talk about the type of resets which are currently in use.

There are two types of reset methodologies which are in current use. 

1) Synchronous Resets

2) Asynchronous Resets

With increasing complexity of chip these days, the systems are moving towards GALS (Globally Asynchronous Locally Synchronous) methodology of using resets. In fact, the clocking methodologies are also following the same trend. I will discuss in more details about GALS in another post when I will discuss the different clocking methodologies under use in different modern day SoCs.

Feedback and comments are welcome.

Next Post : Resets - II

Basics of MOS Devices

Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several layers of conducting and insulating materials to form a sandwich-like structure. These structures are manufactured using a series of chemical processing steps involving oxidation of the silicon, selective introduction of dopants, and deposition and etching of metal wires and contacts.

CMOS technology provides two types of transistors (also called devices):

            A) A n-type transistor (nMOS) and

            B) A p-type transistor (pMOS).

                                                                                                                                  

      Fig 1. Physical Structure and Symbols       a) NMOS Device                  b) PMOS Device                                                

Transistor operation is controlled by ‘electric fields’, so the devices are also called Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply FETs. It is always an integrated structure, there are practically no single individual MOS transistors.

A MOS transistor is primarily a switch for digital devices. Ideally, it works as follows:

            If the voltage at the gate electrode is "on", the transistor is "on", too, and current flow between the source and drain electrodes is possible (almost) without losses.

             If the voltage at the gate electrode is "off", the transistor is "off", too, and no current flows between the source and drain electrode.

Fig 2. Transistor Symbol and switch model

The gate of an MOS transistor controls the flow of current between the source and drain. Simplifying this to the extreme allows the MOS transistors to be viewed as simple ON/OFF switches. When the gate of an nMOS transistor is 1, the transistor is ON and there is a conducting path from source to drain. When the gate is low, the nMOS transistors are OFF and almost zero current flows from source to drain. A pMOS transistors are just the opposite, being ON when the gate is low and OFF when the gate is high.

        

I will discuss  more on the operation of MOS devices in a future post as this was an introduction article. There are many more to come in the series including Fin Fets, Four - Terminal Structures and other modern devices for next generation of Chips.

           

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