This is one of the “many to
follow” quizzes and it is taken from Digital Integrated Circuits by Jan M. Rabaey,
et al. (One of the best books in the world for learning about the Digital
Integrated Circuits). Soon we will have real life circuits(Which are heavily used in the semiconductor industry) to analyze in the quiz section.
Switching Activity
We all know that the dynamic power dissipation
in is given as :
P(dynamic) = α0->1CLVDD2f
Here the factor α0->1 is termed as switching activity (or
the transition activity). The transition activity is a strong function of logic
function (the logic operation being performed by any of the digital gates like
AND, OR, NAND, etc). For gates implemented using static CMOS technology, this
factor is a multiplication of the two probabilities (The subscript 0->1 is there as for static CMOS gates power is only consumed when the output switches from 0 to 1 and not other way round as we have a direct path from supply to the output when output transitions from 0 to 1. More to follow on this in the device section):
P0: The probability that the output will be
“0” in present cycle (or for the matter in any cycle)
P1: The probability that the output will be
“1” in the next cycle (or for the matter subsequent cycle of the cycle under
consideration).
So α0->1 = P0*P1 or
in other words
α0->1 = P0*(1-P0)
If we assume that the inputs to
the N input gates are not related to each other (which is a practical consideration)
and are distributed uniformly over time, then the switching activity is given
as :
α0->1 = (N0/2N)* (N1/2N)= N0(2N – N0)/22N
N0: It is the number of “0” entries in the
output column of truth table for that gate
N1: It is the number of “1” entries in the
output column of the truth table for the same gate
Now for the problem; suppose we
have N input XOR, NOR and NAND gates. Assuming the above assumptions to be
valid what should be the switching activity for the above gates? What will be
the probability if we replace the N input gates with an inverter?
Fig 1. N input NAND Gate
The answers to above questions
are simple and easier to find with the above mentioned details.
Feel free to comment and discuss
on the same.
Comments and Feedback are
welcome.
Hi!
ReplyDeleteI don't think I agree with you on the point that power is consumed only when a 0->1 transition occurs and not during 1->0 transition. During both these transitions current flows to either charge or discharge the output capacitance through pmos or the nmos transistor and during both these transitions an equal amount of energy is spent due to the resistance offered by the transistors. Even in the Rabaey book that you reffered F0->1 means overall switching activity in a cycle, i.e 0 to 1 and 1 to 0. Please correct me if I am wrong.
Hi Saurabh,
ReplyDeleteThanks for pointing this and apologies for replying late as I have been quite busy. :)
You are right when you say that the current either flows to charge or discharge the output capacitance, however when we want to know the power consumption, it is the current taken from the supply that we use for calculating the power(and energy). In the transition from 0->1 the current is taken from the supply(to charge the output capacitance) which contributes to the power, while in the transition of 1->0, the current simply flows from output capacitance to the ground and no current is taken from the supply and hence no power consumption.
Hope that clears the statement made above.
Shubham