As discussed in the last session, we shall see how tunneling is responsible for programming and erasing FG-MOSFETs.
We discussed in the previous session about the 2 states of the FG-MOSFET:
Following is the diagram of FG-MOSFET which we analyzed in the last session:
When we program the device (20 V at Control Gate and 0 V at Substrate), because of the downward electric field, the electrons are tunneled upwards through the Lower Oxide Layer into the Floating Gate. In the figure below, the black arrows downward denote the applied electric field through voltage on Control Gate. The read arrows upward show the direction of movement of bulk electrons from the p-type substrate.
So what actually happens at the p-type substrate -TO- oxide - TO- Floating Gate interfaces which causes electrons to even cross the oxide layer in between?
I hope you are familiar with the energy diagrams. Below you can see the energy diagram of the above mentioned interface at equilibrium.
We discussed in the previous session about the 2 states of the FG-MOSFET:
- Binary 0 : Programmed => Electrons present in Floating Gate
- Binary 1 : Erased => Electrons removed from Floating Gate
Following is the diagram of FG-MOSFET which we analyzed in the last session:
When we program the device (20 V at Control Gate and 0 V at Substrate), because of the downward electric field, the electrons are tunneled upwards through the Lower Oxide Layer into the Floating Gate. In the figure below, the black arrows downward denote the applied electric field through voltage on Control Gate. The read arrows upward show the direction of movement of bulk electrons from the p-type substrate.
So what actually happens at the p-type substrate -TO- oxide - TO- Floating Gate interfaces which causes electrons to even cross the oxide layer in between?
I hope you are familiar with the energy diagrams. Below you can see the energy diagram of the above mentioned interface at equilibrium.
The following notations are used in the diagram:
The following layers of the FG-MOSFET are shown in the diagram:
- n+ type Control Gate : made of n+ type Polysilicon
- Upper Oxide Layer: made of silicon dioxide or oxide-nitride-oxide (ONO)
- n+ type Floating Gate : again made of n+ type Polysilicon
- Lower Oxide Layer: made of silicon dioxide
- p type Semiconductor
Now, here comes trick! I guess you must have noticed the very less thickness of Lower Oxide Layer as compared to Upper Oxide Layer. The high voltage (20 V) causes a huge drop of Fermi Level of the Floating Gate, as a result of which, the potential barrier width that an electron has to cross reduces (Note the triangular barrier developed adjoining the conduction band of p-type semiconductor). On the other hand, there is not much bending of barrier in the Upper Oxide Layer because of its thickness. So the thin potential barrier in the Lower Oxide Layer provides a path for electrons to tunnel through it. And consequently, the electrons get trapped in the Floating Gate.
This tunneling in FG-MOSFETs is called Fowler-Nordheim Tunneling (F-N Tunneling).
After going through lot of mathematical manipulations and assumptions, we obtain the following relation for tunneling probability of an electron for F-N Tunneling:
The probability equation above is a negative exponential curve [ f(x) = exp(-x) ] like below (shown for x > 0):
So, the probability that a particle can tunnel through the potential barrier increases as x decreases and gets closer to x = 0.
In our tunneling equation, the probability will hence increase if the whole factor
reduces to a very small value. This is achieved by applying a high voltage (20 V) and hence a high electric field E. Hence, by applying this high electric field, we actually increase the probability of tunneling of an electron into the Floating Gate, hence causing the program operation to happen.
Another conclusion : a small voltage ideally cannot disturb the electrons inside the Floating Gate as a small electric field cannot increase the probability of tunneling of an electron.
I guess you have a brief idea now as to how the tunneling causes the program operation in FG-MOSFETs to happen. It is easy to deduce the band diagrams in erase operation: the bending of oxide layers happens just the reverse and electron crosses from Floating Gate to the Semiconductor.
Now, how will you detect whether there are electrons or not in the Floating Gate? In other words, how will you read whether the FG-MOSFET contains a binary 0 (programmed) or binary 1 (erased)?
So, let us discuss the Read operation in FG-MOSFET in the next session, now that we have completed Program and Erase operations.
Till then, "Anyone who is not shocked by the quantum theory has not understood it" ---- Niels Bohr.
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