Quiz #1 Switching Activity Calculation for N input gates

This is one of the “many to follow” quizzes and it is taken from Digital Integrated Circuits by Jan M. Rabaey, et al. (One of the best books in the world for learning about the Digital Integrated Circuits). Soon we will have real life circuits(Which are heavily used in the semiconductor industry) to analyze in the quiz section. 

Switching Activity

 We all know that the dynamic power dissipation in is given as :

P(dynamic) = α_0->1C_LV_DD²f

Here the factor α_0->1 is termed as switching activity (or the transition activity). The transition activity is a strong function of logic function (the logic operation being performed by any of the digital gates like AND, OR, NAND, etc). For gates implemented using static CMOS technology, this factor is a multiplication of the two probabilities (The subscript 0->1 is there as for static CMOS gates  power is only consumed when the output switches from 0 to 1 and not other way round as we have a direct path from supply to the output when output transitions from 0 to 1. More to follow on this in the device section):

P₀: The probability that the output will be “0” in present cycle (or for the matter in any cycle)

P₁: The probability that the output will be “1” in the next cycle (or for the matter subsequent cycle of the cycle under consideration).

So α_0->1 = P₀*P₁ or in other words

α_0->1 = P₀*(1-P₀)

If we assume that the inputs to the N input gates are not related to each other (which is a practical consideration) and are distributed uniformly over time, then the switching activity is given as :

α_0->1 = (N₀/2^N)* (N₁/2^N)= N₀(2^N – N₀)/2^2N

N₀: It is the number of “0” entries in the output column of truth table for that gate

N₁: It is the number of “1” entries in the output column of the truth table for the same gate

Now for the problem; suppose we have N input XOR, NOR and NAND gates. Assuming the above assumptions to be valid what should be the switching activity for the above gates? What will be the probability if we replace the N input gates with an inverter?

                                                                   Fig 1. N input NAND Gate

The answers to above questions are simple and easier to find with the above mentioned details.

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