Resets - II

Continuing from our last article, Resets - I , this article discusses the synchronous resets mentioned earlier and evaluates its pros and cons.

Before continuing forward, a basic knowledge of the "Flip Flop" is assumed.

Synchronous Resets

Synchronous is derived from two terms “syn” meaning “same” + “chronos” meaning “time” and how do we denote time in our systems? The answer is Clocks. So going by the name, this reset occurs when the reset is HIGH/LOW (depending on the type of reset) at a rising/falling clock edge (again depending on whether the flop is positive edge triggered or negative edge triggered). If the reset goes high (Assuming reset=1 put Q=0) in between any time t, t+T (where T is the time period of the clock) and comes back to “0”, the reset will not be registered. Or in other words there is no difference between the D signal (Assuming a D type flop which is the industry standard) and the reset signal as both of the signals are sampled at the positive/negative edge of the clock.

Consider the diagrams below and it will make more sense:

Fig 1. D Flip Flop

                                              Fig 2. Timing Diagram for D Flip Flop in fig1.

Note that in above diagram we have assumed a Zero delay model for each of the signals (Which is a deviation from the real world as it has delays, I will come back with more on this)

From above diagram it is easier to see that No matter what the value of D_flop (which is the D input of the flop ) while the sync_reset is high, the Q_flop will be "0". Once the reset has been removed, Q_flop follows the D_flop.

The plus points of the synchronous reset are clearly visible:

1.      It helps in glitch filtering (If they do not occur near the clock edge then the glitch will not cause any harm to the circuit).

2.      Also the (not so visible point) is that the flop circuit is simple and hence consumes less area.

3.      The resulting system is completely synchronous

The negative point lies in the plus point themselves:

1.      It requires a clock in order to be sampled.

2.    The applied reset will have to strictly adhere to the requirements of setup and hold times (provided in the “SPEC” sheet of the Flop) so that there are no timing issues.

3.     One big problem which arises while using this kind of reset (because of the fact that they are similar to data signals) is the synthesis. The synthesis tool may not be able to differentiate between data and the reset as both are being sampled on the clock edge. It becomes necessary then to tell the tool to add certain “directives” which tell it that the input to “S or R” pin of the flop is a “set or reset” signal.

4.   Also it may happen that the reset signal becomes the fastest timing path and then would need a timing closure  as it would be the critical path, which we generally don’t want. 

Synchronous designs have been the preferred design for designers for the last few decades but with increasing 

complexity newer approaches are being adopted by the industry (GALS being one of them which I mentioned in

an earlier post).

Hope you liked the article.

Your feedback and comments are welcome.

Upcoming Post : Reset - III

Resets - I

Why do we need RESETS?

Resets in any SoC (or for the matter in any complicated chip) are required to put it in a known or sane state. An example of resetting is when our mobile phone hangs we generally shut it down so that it comes back to normal state (Shutting down is equivalent to resetting it). Similarly resets are required so that any SoC can be brought back to a default state.

                                                           Fig 1. D type Flip Flop with Reset Pin
During the design phase we apply reset while simulating the design, the resets are used to ensure that the initial state of system is known and then we force them into the other states for the purpose of simulation. Also they ensure that the hardware is in a known state as circuits have no inbuilt method for self- initializing them. For a real hardware system or board, when we power up the system we reset everything so that we know which register contains what before we start any other operation on it. A typical modern day SoC contains hundreds of register and knowing the state of each register is almost impossible unless we reset them in the start and then put them into operational states.

Another use case of reset is in watchdog counter circuits. I will talk about watchdog circuits in a later post, but for now I can tell that watchdog circuits are used to ensure that the circuit does not enter into a deadlock state. For e.g assume that two processes are running in parallel on a system. Let us call them Process A and Process B. Process A wants to use a system resource and it issues a request for using it and at the same time Process B wants to use the same resource and it also issues the same request (resource here refers to a hardware resource). Since both the requests are issued at the same time, each process will assume that the resource is busy and being used by another process and this will go on indefinitely with neither process using the resource. In order to get out of such a situation we have a counter circuit which times out after a certain number of clock cycles and then either of process can use the resource.

Above was one example of a deadlock, there are other examples as well, I will discuss about them in some future post. For now let us talk about the type of resets which are currently in use.

There are two types of reset methodologies which are in current use. 

1) Synchronous Resets

2) Asynchronous Resets

With increasing complexity of chip these days, the systems are moving towards GALS (Globally Asynchronous Locally Synchronous) methodology of using resets. In fact, the clocking methodologies are also following the same trend. I will discuss in more details about GALS in another post when I will discuss the different clocking methodologies under use in different modern day SoCs.

Feedback and comments are welcome.

Next Post : Resets - II