VLSI/ASIC Job Opportunity in Bangalore

Hi All,

We are looking for candidates interested in VLSI/ASIC having relevant work experience.

Location : Bangalore

The Job Description (JD) is below.

Please mail your resume/cv @ socasicdesign@gmail.com with following subject line : [JD Applying for]_[Years of Experience]_experience

JD :

Design Engineer
Required skills and knowledge :
1. BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE
2. Knowledgeable in System Verilog RTL coding, PERL, Timing
3. Strong Knowledge on the IP development flow is must
4. FPGA Prototyping of the IP is a plus
5. Domain expertise in Networking protocols/Interface protocols like PCIe, USB, SATA
6. Working knowledge in Multi-clock domains and Power domains is an added advantage
7. Good Communication skills with ability and desire to work as a good team player

Verification Engineer
Required skills and knowledge :
1. BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE
2. Design and develop testbenches using HVLs like System Verilog, Specman, etc
3. Deep expertise in Verification Methodologies like OVM, UVM, VMM
4. Should have experience in creating verification environment and test plans
5. Domain expertise in Networking protocols/Interface protocols like PCIe, USB, SATA / SoC Verification is a plus
6. Familiarity with Scripting languages
7. Good communication skills with ability and desire to work as a good team player

Converting from a 2's Compliment Representation to Decimal Representation

If you are into designing arithmetic circuits, or interacting with digital systems, you would have definitely encountered 2's Compliment Scheme for representing the integers in the system. 

Most of the modern day computers; including the most advanced of SoCs in today's existing systems or the one's which will come in future; use predefined macro cells with the logic for doing these operations.

You will not be designing these cells but you'll definitely be using those cells from the standard libraries. The first question that arises here : If these designs already exist and I have to only use them, then why do I care how it is implemented?

Yes, you are right, it doesn't matter how it is implemented but what matters is to understand how the concept works. In other words, one should simply understand how the arithmetic block works or what is the output it should give provided a set of input.

This post is about converting from a 2's compliment representation of binary number to an integer representation. 

The assumption here is that one understands the base system for representing any number.

If we are representing a  number with fixed number of bits in binary representation, then the leftmost bit is treated as the Most Significant Bit (or MSB). In 2's Compliment Notation, this bit decides the sign of the decimal number. The agreement is : If the MSB is 0 then it is a positive integer, else it is a negative number.

Now if the MSB is 0, then it is relatively straightforward to calculate the decimal number as shown in example below (for the sake of explaining we will consider 6 bit binary representation) :

Consider the number 001100, the equivalent decimal number will be equal to 1*2^3 + 1*2^2 + 0*2^1 + 0*2^0 = 12. 

We simply multiplied the corresponding bits with the appropriate position in terms of powers of 2 like in the decimal system.

Now let's see how do convert the number when MSB is 1. 

Consider the number 101100, the equivalent decimal number will be equal to (-1)*2^5 + 0*2^4 + 1*2^3 + 1*2^2 + 0*2^1 + 0*2^0 = -32 + 12 = -20.

The trick here is simple. The position of the MSB remains the same(i.e. the power of 2 associated with the position stays the same. In above example the power of 2 associated with MSB is 5) but we associate a weight of (-1) with the bit.

The trick above is applicable to calculation of positive integers also (Please note that in case of positive integers, the value of MSB is 0 so the contributing factor comes out as (-1)*0*2^(MSB-1) = 0).

Hope that above trick will speed up your calculations while handling 2's compliment representation.

Provide your feedback and responses in comments below !!

Till the next post !!

Video Courses on "Computer Architecture" from MITx

It has been a long time since we posted links to courses in the field of Computer Architecture.

Guess what, there are some exciting courses coming up on Edx from MITx on the said field. If you are interested in the field of Digital Design or intend to design some of the cool systems which are used world wide, these courses are a good starting point to learning the underlying concepts.

These are also helpful if you intend to enter into the semiconductor industry(or maybe thinking of adding a new skill set to your portfolio) or wanting to refresh the basics or maybe thinking of preparing for interviews.

These courses are a part of Computation Structure series where you will be designing your own processor after learning the concepts.

Kindly do enroll and provide your feedback on the courses.

The starting dates and course names are also provided :


Computation Structures Part 1: Digital Circuits - starts September 6th
Computation Structures Part 2: Computer Architecture - starts November 29th
Computation Structures Part 3: Computer Organization - starts February 8th (2017)

See you there!! :)

PS : You will also get a certificate from MITx if you enroll in the paid version of the course.

Verification | System Verilog | Universal Verification Methodology - I

Over the last few months, I have been working on verification of SoCs using System Verilog/Universal Verification Methodology (or popularly known as SV/UVM in the VLSI Industry). I thought that I will create a list of sites, links to the important documents from various sources which I have used to develop my skill set in the said area. 

Also, I will try to list the interview questions which are highly useful and generally asked by most of the VLSI Companies hiring for SV/UVM/Verification skill set. 

One of my friends has done a very good job of compiling a library to learn about SV/UVM on his site Verification Guide . One of the best thing about this site is that you can compile the code and run it on EDA Playground, a free online tool provider for running simulation/synthesis and many other utilities. EDA Playground is now a part of Doulos.

Verification guide provides you with lots of examples and also to test these examples by making the changes to the code on EDA Playground.

Do let me know your feedback, if you found the examples to be useful.

Before I close on this article, one important remark I would like to make is that knowing the language alone does not close the case. Language is just a tool to solve a problem. It is the problem solving ability that matters. :)

Please do look out for this section as there are many articles coming up in this space(Along with generally asked interview questions)

Closing with the lines of  John Johnson, “First, solve the problem. Then, write the code.” 

Till next post!!!

Free Timing Diagram Drawing Tools

In the VLSI industry, it is a requirement to come up with timing diagrams for the operations of circuits, blocks and IPs. It is also required at times about how the blocks interact with each other. This timing information is captured using waveform in the Design Specification docs and also in testplan many a times. In such a situation there is a requirement to draw the diagrams showing the relations ship between different signals and their alignment with the clock. 

Though you can get the job done using Microsoft Powerpoint/Microsoft Visio/Microsoft Excel, however, there are multiple online free tools available to make timing diagrams in the format we want(and also in lesser time than above and hence contributing to our productivity).

I am listing some of the tools which can be used(My personal favorite is WaveDrom. It even has a dedicated SNUG paper for it)

• WaveDrom - It can be installed in your computers or can be run online to create timing diagrams. It creates timing diagram using simple textual inputs (basically a javascript).  Here's the link to SNUG paper on it. The link has a tutorial also and it is very easy to use.Below is the sample image generated from WaveDrom :

                                                                     Fig 1. Timing Diagram from WaveDrom

• DrawTiming - It is also a very simple tool with a command line interface which allows you to write scripts(pretty intuitive). Below is a sample image from the tool site :

                                              Fig 2. Timing Diagram from DrawTiming

• Timing Editor - It is another free waveform editor which can be used to create timing diagrams.

• Timing Diagram Font - This software allows to generate timing diagrams in MS Word font. An example GIF generated using above tool is provided below(from the given link only)

Fig 3. Timing Diagram from Timing Diagram Font

I found above tools pretty interesting to play with and they save time while working.

I hope above tool will also help in your journey.

Let me know if you know of any other tool which is simpler to use than above. 

Till next post !!!

***Please note the images put in above figures are taken from the tool sites respectively. I dont have a copyright on above images.

Online course on "Computing Technology"

For all the computer enthusiasts (and those who want to learn about the basics of computer design), there is an online course which started recently. It covers most of the basics of processor design starting from digital electronics till the programming end(the different layers of development and also the various jobs that are built around those layers :) ).

The link to the course is  : The Computing Technology Inside Your Smartphone

The course, though may be named as the "The Computing Technology Inside Your Smartphone", covers the fundamental of computer architecture with the case study of Qualcomm's Snapdragon processor which is used in plethora of smartphones in modern day(Smartphones from a wide range of companies like Samsung, HTC, Lenovo, Xiomi, etc use Qualcomm's snapdragon SoC{SoC is semiconductor industry jargon for System-on-Chip} ).

Kindly enroll in this course as it starts from the basics and gives out a strong idea about how such a large computer (from the PC era) has shrunk to size where it can be accommodated in our pockets(the smartphone era).

Even if you do not know anything about the electronics, this course can definitely help lay a foundation of electronics. Moreover you will be designing one such processor yourself.

Cheers !!!

Happy Learning !!! :)

 

Video Series on "Foundation of Computer Science"

It has been a long time since we were last active on the blog. Kindly accept our apologies for that as we have been a lot busy with our work life, but we are back and as mentioned in our last post that we would be providing some useful links to build upon your knowledge in various domains of electronics and computer science, here are the few good links for learning more about these fields :

If you want to learn about Foundations of Computer Science you can join the courses offered by MIT (Massachusetts Institute of Mechnology) under edx/Xseries section. About the courses in Foundation of Computer Science (quote from the xseries itself : https://www.edx.org/xseries ) :

"The Foundations of Computer Science XSeries, offered by the M.I.T. Department of Electrical Engineering and Computer Science, is a sequence of courses that introduce key concepts of computer science and computational thinking. Students apply these concepts and build their engineering skills by completing software and hardware design problems. Additionally, students test their understanding by taking a series of exams"

Though there are seven courses in the series, these cover a good amount of Digital Electronics as well.
Currently two of the 7 courses are ongoing(started this Monday and Tuesday) and you can enroll in them to learn the basics of Digital Design and computer science concepts using Python.

Here are the links to those :

1. 6.00.2x Introduction to Computational Thinking and Data Science
2. 6.004.1x Computation Structures: Digital Circuits 

It is not mandatory for you to join the courses with the fees, you can also pursue the course freely by signing up for the honor code certificate. All you need is an internet connection.

I will keep updating when other courses of the series start.

If you have any doubt regarding what all courses(related to the field of Electronics or Computer Science) to do you can comment here, for queries related to the above courses you can ask them in the discussion forums (or here as well)

Till then, happy learning. :) 

Message from SOCD Team

Hi All,

After an overwhelming response from people who want to learn the basics of electronics and are in search of resources for learning new things in the area of SoC design, we thought that it would be a good idea to pour in a basic learning curve for all the "Electronics Enthusiasts". Motivated by the appreciative response from people, we have added another menu button which will contain links to various important lectures which can be used as a road-map for learning the basics of SoC design and related fields.

Under Video Tutorials tab above you will find blogs which will contain links to various courses that can be undertaken to learn SoC design, starting from scratch. Also this section will contains links to videos in various fields of SoC design and application including VLSI Digital design, Computer Architecture, Analog Design, Embedded systems, languages like Verilog/System Verilog, etc.

We do not guaranty that you will become instant success after going through the videos, but we do guaranty that given proper amount of time, one can become a virtuoso of the field the person chooses to work on. It will take time but the time spent will be highly rewarding and lead to a start of new learning curve on which you can build upon.

Also these lectures (if the mentioned pattern is followed) will be helpful when you join the industry of your preference (these will be helpful in your interviews as well). We found these lectures awesome and highly satisfying, hope they do the same for you. With the Semiconductor market being highly competitive, it is really difficult for a fresher to land a job in the Industry, but with proper planning and using the correct resources there are vast amount of opportunities in the field. In fact most of the companies have so many vacancies but they are not able to find the appropriate talent among a large pool of Electronic Engineers because of lacking the appropriate knowledge and basic skill set.

Putting these tutorials together(and the blogs) is our means of providing the knowledge which is relevant for any candidate which is aspiring to land a job in the Semiconductor Industry.

Hope all the effort will be really helpful for the learners !!!

Kindly like the facebook page of the blog for getting updates. The link is provided below :

                                                                       SoC-ASIC-Design Facebook Page

or you can subscribe the blog by clicking on the subscribe option in the right side of the window.

Till the next post.

Cheers !!!!

SOCD Team

Standard Clock Gate Cell

Moving ahead from my last article on Clock gating(You can read the previous article here : Low Power Techniques - Clock Gating), this small article introduces the standard “Clock Gate Cell” This cell is available to all the designers in semiconductor industry along with the other standard cells in their libraries. It is good to recognize early that clock and power are mingled up and clocks provide a good deal of avenues for saving power. So knowing more about clocks is always a plus to person interested in designing "Power Aware Circuits".

In the last article, we saw that there was a glitch in “certain cases”, when we gated the clock. These “certain cases” led to the development of this cell. If you look more closely at the waveform given in last article (reproduced below for convenience), the glitch will always be there whenever the enable signal goes down and the clock is high (high as in logic 1) .

Fig 1. AND Gate as a Clock Gate and Problem of Glitch (Reproduced from Low Power Techniques- Clock Gating)

The above observation is simple enough to propose a solution for the glitch problem in AND gate. Fig 2. shows the clock gate cell. 

Fig 2. Clock Gate Cell

This cell stops the clock without any glitch in the output.  And how does it do that? It utilizes a LATCH for this purpose. 

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Latching Mechanism

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A latch is a level sensitive device in which the output is same as input till its Enable signal is at a particular logic level. Generally logic 1 is the chosen level for this matter. The output traces the input till the Enable signal is logic 1 and as enable is switched to logic 0, the output retains the last value it captured from the input till the next enable comes where it starts tracking the input again.

------------------------------------------------------------------

Latching Mechanism as used in Clock Gate Cell

------------------------------------------------------------------

For clock gating purpose the enable signal of latch is tied to the inverted clock signal (Clk_in) so that output changes only when the clock is at a particular logic level (which is logic 0 in our case). So it is easy to see that we can pass Enable signal and the changes will be recorded only when the logic level is low (or logic 0) and then AND this with the clock signal. This will ensure that that the Enable low is recorded only when the Clk_in is low and hence no glitch in the output.

Note that we have inverted the clock before sending it to the latch so as to ensure that the latch is sensitive to logic 0 of Clk_in (since the latch itself is sensitive to logic 1). Before I proceed further, I would like to point out that a latch is a very powerful tool available to designers and it is used in multiple circuits (it will be a hot topic in some of the coming articles). With above cell Fig 1. modifies to Fig 3. as below :

Fig 3. Timing Waveform for Clock Gate

In the above figure notice how the enable edges which happened during the clock high have been translated or rather delayed in the clock low domain.

We can use this cell to TURN OFF an entire clock domain or TURN OFF only a few flops. It is entirely on designer that how much power he wants to save and according to that we have levels of clock gating in any SoC. Also note that these Enable signals are controlled by Finite State Machines (FSMs) which trigger based on inputs from other FSMs in SoC.

A small point to all the above information is : Clock gate is a HW means to control the clock signal there are software means as well in which we program the PLL itself to control the entire clock tree. 

I conclude this article here with these lines of Dr. Thomas Fuller :

"Let not thy will roar, when thy power can but whisper"

Low Power Techniques : Contemporary Strategies - I

Most of the SoC designs for mobile domain(by Mobile Domain, I mean the devices being used in SmartPhones, tablets, laptops, or any gadget which can be carried from one place to another easily) require it to consume low power while performing operations at the same time.

This article discusses the various contemporary techniques (in brief) employed by the Design companies in coming up with such complex SoCs. Before we proceed any further, I would like to differentiate between two terms which are often used interchangeably in the industry these days. They are : Low Power and Power Aware

There is a difference in the two terms which I mentioned above. Be known that “Low Power is not the same as Power Aware.”

Difference between Low Power and Power Aware Techniques

Low Power (in the context of these devices) means that the device will consume low power owing to the way it is implemented. One example for this would be the use of High Threshold (High Vth) MOS transistors in the design which has lesser leakage and performs slower than the Low Vth transistors which are leaky.

Power Aware, on the other hand, implies that the SoC or device itself is intelligent enough to shut down or turn-off the units which are not required while performing a particular operation or the device knows when to operate at a lower frequency or in a low power consuming mode/state.

Contemporary SoCs are a mingled version of Power Aware as well as Low Power Techniques to have an optimum performance and power consumption at the same time. Due to excessive power consumption by these small devices, a new parameter has emerged as a metric for SoCs. It is Performance per Watt or in Industry Lingo it is Perf/Watt. Know that this number will be different for different types of tests/benchmarks we run on the design. Generally the worst case Perf/Watt should be reported.

So here I go on listing and summarizing the techniques that are being used.

I leave it to you to categorize the technique as low power or power aware. J

The first and simplest to understand is MTCMOS

1.      MTCMOS (Multi – Threshold CMOS)

Fig 1.  Types of MOS Transistors with different Vt

 As mentioned above, this technique is highly useful in reducing leakage power. Every company has its own standard cell library and a standard library is provided by “The Foundry” as well. This library (the one provided by the foundary) contains transistors with varying thresholds or different Vth’s. Since low Vth implies(these cells are termed as LVT cells; LVT standing for Low Vth) higher leakage but high speed, we tend to use them in timing critical paths (What is a timing critical path??) or in other words, the path which has the largest delay (arising from flops, combo logic) in it. For all other paths or in between logic, we use the cells with medium Vth(SVT for Small Vth) or high Vth(HVT for High Vth) which has lower performance but are highly tolerant to leakage power. In fig 1b., the solid dashed line in the gate is used to depict that it is a high threshold device. The Vth of the transistor is changed by varying the oxide (SiO2) thickness in the MOS transistor and hence the solid line for showing thick oxide layer in fig 1b. 

For details you can visit this article again :  Basics of MOS Devices 

2.      Multiple Supply Voltages

Fig 2. A SoC with Multiple Voltage Islands

Kindly note that above figure is arbitrarily drawn and bears no resemblance to any existing SoC. 

For a long time the industry has been dreaded by the dynamic power consumption which is a strong function of the operating voltage, frequency and load capacitance, given by the relation :

P_dyn = C_LVDD²f

Note that in above equation I have not considered the switching factor.

As per above equation if we reduce the operating voltage by 2 by keeping all the other things constant, the dynamic power would be reduced by a factor of 4. This simple approach is used in coming up with SoCs which have different voltage islands in it. The different parts of the SoC operate on different voltages, and of course on different frequencies. As an example the audio unit in any SoC can operate at lower frequency than the display unit and hence we can use different voltages for these two types of IP’s. Such scenario is depicted in figure above.

I’ll talk about more about the remaining techniques in a follow - up article.

Till then, “It is not the end but a start of new era of revolution”.

Low Power Techniques : Clock Gating

Disclaimer : All the articles are written with an assumption that the reader has a basic knowledge of Boolean Gates and digital elements.

In this article, the key focus of discussion would be clock gating and its impact on the design on modern day SoCs. Clocks could be considered as the Arteries (or Veins so for the matter) of the entire SoC and clock source being the heart of any SoC. All the IP’s like CPU, Audio, Display, USB, etc require a clock to function. It is the “CLOCK” which gets to decide the maximum speed of operation for any SoC (Here I am not considering the throughput increase due to the various kinds of architectures employed in designing the SoC) and hence special attention should be given to this signal.

Another reason why this signal should be given more attention is due the fact that it is the highest toggling signal in any SoC and therefore consumes the largest fraction of entire SoC power. In a typical SoC for mobile application, the clock tree consumes 30-40% of the power (Yes, this number can be more depending on the Clocking architecture employed).

Clock gating is a technique to turn the clock OFF depending on the requirement or the use case. How this is achieved is the main focus of this topic.

There are essentially two ways to gate the clock. One through hardware control and one through software control.

The software control is through registers which are used to control the PLL or DLL or any other clock source that we may have. We turn the PLL/DLL/Source off (which is in itself at times a complex process) by following a specific sequence. Turning of the source is a method to gate the trunk of the clock tree (I’ll talk about the Industry lingo on clocks in an upcoming article. Kindly bear with us on terms like trunk, branch, etc).

It may happen that in some of the cases we want to shut only a branch of the trunk. This is the point where hardware control comes in picture.

This article (and some subsequent articles) will discuss on hardware control of the clock.

Below is shown a free running clock :

Fig 1. Free Running Clock

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How can we actually stop it based on some control signal say “enable”?

---------------------------------------------------------------------------------------

Yes, you got it right, we need to AND the two signals and put the enable to be at “1” when we need the clock and “0” when we don’t want the clock output for any IP.

The figure below shows a simple AND gate being used as a gate.

                                       Fig 2. AND Gate as a Clock Gate and Problem of Glitch

So do we actually use this “AND” gate in our SoCs to gate the clock from reaching to any IP?

You guessed it right. No, this is not the standard cell which any modern day SoC use. The reason is clear from above figure itself. If the enable signal changes while the clock is high, this will lead to a runt pulse termed as “Glitch”. A glitch is harmful for any SoC as it can lead to unknown states or the states which we don’t want our system to be in. For now, I’ll leave the glitch to a-not-so-far-in future article.

I’ll discuss about “Clock Gating Cell” in the next article.

Till then, Enjoy!!! 

SESSION 3: Reading from FG-MOSFETs: Part- 1

Hello everyone. In previous sessions, we have discussed the method to program and erase an FG-MOSFET. 

And programmed state corresponds to binary 0, whereas erased state corresponds to binary 1.

Now the question here lies: how will you get to know whether your FG-MOSFET has a binary '0' or a binary '1' stored in it? In other words, how will you read the data present in FG-MOSFET?

------------------------------------------------------------
The answer lies in the threshold voltage.
------------------------------------------------------------

Now suppose I connect an FG-MOSFET to two batteries, one VGS between gate and source, and the other VDS between drain and source. See the figure below.

So the voltage VGS provides an electric field in the direction shown by the red arrows in the figure below:

Because of this electric field, the holes at the interface of p-type semiconductor and oxide layer are repelled away. The electrons appear at this interface from bulk of p-type semiconductor, thus forming an n-type channel between n-type source and n-type drain. Since this n-type channel is formed from p-type semiconductor, it's called inversion channel.

What role does VDS play here? It provides the field from Drain to Source, thus pulling electrons from Source to Drain via the inversion channel formed by applying VGS. 

You may visualize the above process in the video below. The small red circles represent the holes in p-type semiconductor and the small green circles represent the electrons. Note the inversion channel formation in the video.

In the above video, the flow of electrons indicates the flow of current in external circuit. 

Now, what if the voltage VGS  was not sufficient enough to create the inversion channel? Then obviously, current will not be able to flow.So for every FG-MOSFET, there is a particular value of VGS, only above which the inversion channel is formed and conduction takes place. This value is called threshold voltage, VT.

So, the conclusion till now is: 

The following graph represents the above relation between current IDS and VGS:

As we might intuitively conclude that increasing VDS shall also increase the current IDS (the greater the VDS, greater the pull on electrons via the channel), but does it go on forever?

Reason: Channel pinch-off

Let us see what is channel pinch-off and why does it occur in the next part of this session.

Eventually you will see these concepts clubbing together to build up the concept of reading from an FG-MOSFET.

Till then : "Thresholds are not the ends! Something definitely lies beyond them"

Find Previous Post here : SESSION2: Tunneling for Programming and Erasing FG-MOSFETs

The Myth of Area Downsizing in SoCs

Why do we fuss so much about optimizing the area?

Why do we want to optimize the design and learn various design techniques which help in reducing the area to obtain the same functionality?

This is the topic of discussion for this article.

Any chip is fabricated by following a series of steps like lithography, oxidation, etching, metal disposition, ion implantation, etc. These steps are performed on a silicon wafer (which is generally circular owing to the processes that we use to obtain pure silicon which leads to long cylinder of wafers (called Silicon Ingots) which is then sliced to obtain the silicon wafer). A single wafer can contain many dies (which we package and obtain our chips from).

A diagram is shown below which shows the wafer (sliced from the cylinder) and the dies in the wafer:

Fig 1. Silicon Wafer and Ingot,  1a. A Wafer depicting dies ,

1b. A cylindrical silicon ingot which is sliced to get various wafers

Fig 2. Silicon wafers with different die size and defects

Note that it is these dies which we package and obtain our chips from. You can view the actual Silicon Ingot at this link: Making of Silicon Ingots

From figure 1 and figure 2 it is clear that if we want more chips from a wafer we need to have a small die size or in other words we can say that,

                                         “Yield has an inverse relationship with die size”.

The more the die size, lesser is the yield for the wafer with same sizes.

Another thing to note is that if we keep the die size to be constant then in order to increase the yield we will have to increase the wafer size.

So do we increase the wafer size to obtain higher yield if we can’t reduce the area further?

The answer is partly yes.

We cannot increase the wafer size indefinitely as it gets unstable after certain size. Currently the semiconductor industry has been able to hit wafer sizes 6 inch, 12 inch and 18 inch. Plenty of research is going on for increasing the wafer size.

Another thing which I have not mentioned above in regards to yield is that having a lesser area has other perks as well. The above mentioned processes like lithography, ion implantation, etc are not perfect and they introduce defects in the chip leading to faulty chips and thereby lesser yield.

How does having a lesser area helps?

It is said a picture is worth thousand words. So considering Fig 2., it is obvious that having a lesser die area will definitely contribute to higher yield considering that the process introduced defects(In Fig 2. above, the red dots corresponds to defective dies) are similar. If we calculate the yields from Fig 2. , it is clear that in 1^st wafer the yield would be 2/4 = 0.5 or 50% (I have ignored the area which is not used in any die, the blue part, just so to be abstract) and in 2^nd wafer it would be 22/28 = 0.78 or 78%.

Clearly the yield is greater in 2^nd wafer.

So the next time you hear people trying to reduce the area, you will definitely have some idea on why the area reduction is important for any SoC or ASIC.

Till then "Try to learn something about everything and everything about something - Thomas Huxley".

Feedback and comments are welcome.

SESSION 2: Tunneling for Programming and Erasing FG-MOSFETs

As discussed in the last session, we shall see how tunneling is responsible for programming and erasing FG-MOSFETs.

We discussed in the previous session about the 2 states of the FG-MOSFET:

1. Binary 0 : Programmed => Electrons present in Floating Gate
2. Binary 1 : Erased => Electrons removed from Floating Gate

Following is the diagram of FG-MOSFET which we analyzed in the last session:

When we program the device (20 V at Control Gate and 0 V at Substrate), because of the downward electric field, the electrons are tunneled upwards through the Lower Oxide Layer into the Floating Gate. In the figure below, the black arrows downward denote the applied electric field through voltage on Control Gate. The read arrows upward show the direction of  movement of bulk electrons from the p-type substrate.

So what actually happens at the p-type substrate -TO- oxide - TO- Floating Gate interfaces which causes electrons to even cross the oxide layer in between?

 I hope you are familiar with the energy diagrams. Below you can see the energy diagram of the above mentioned interface at equilibrium.

The following notations are used in the diagram:

The following layers of the FG-MOSFET are shown in the diagram:

1. n+ type Control Gate : made of n+ type Polysilicon
2. Upper Oxide Layer: made of silicon dioxide or oxide-nitride-oxide (ONO)
3. n+ type Floating Gate : again made of n+ type Polysilicon
4. Lower Oxide Layer: made of silicon dioxide
5. p type Semiconductor

So, when a high voltage, say 20 V is applied to the Control Gate, the energy bands transform as shown in the figure below:

Now, here comes trick! I guess you must have noticed the very less thickness of Lower Oxide Layer as compared to Upper Oxide Layer. The high voltage (20 V) causes a huge drop of Fermi Level of the Floating Gate, as a result of which, the potential barrier width that an electron has to cross reduces (Note the triangular barrier developed adjoining the conduction band of p-type semiconductor). On the other hand, there is not much bending of barrier in the Upper Oxide Layer because of its thickness. So the thin potential barrier in the Lower Oxide Layer provides a path for electrons to tunnel through it. And consequently, the electrons get trapped in the Floating Gate.

This tunneling in FG-MOSFETs is called Fowler-Nordheim Tunneling (F-N Tunneling).

After going through lot of mathematical manipulations and assumptions, we obtain the following relation for tunneling probability of an electron for F-N Tunneling:

The probability equation above is a negative exponential curve [ f(x) = exp(-x) ] like below (shown for x > 0):

So, the probability that a particle can tunnel through the potential barrier increases as x decreases and gets closer to x = 0.

In our tunneling equation, the probability will hence increase if the whole factor

reduces to a very small value. This is achieved by applying a high voltage (20 V) and hence a high electric field E. Hence, by applying this high electric field, we actually increase the probability of tunneling of an electron into the Floating Gate, hence causing the program operation to happen.

Another conclusion : a small voltage ideally cannot disturb the electrons inside the Floating Gate as a small electric field cannot increase the probability of tunneling of an electron. 

I guess you have a brief idea now as to how the tunneling causes the program operation in FG-MOSFETs to happen. It is easy to deduce the band diagrams in erase operation: the bending of oxide layers happens just the reverse and electron crosses from Floating Gate to the Semiconductor.

Now, how will you detect whether there are electrons or not in the Floating Gate? In other words, how  will you read whether the FG-MOSFET contains a binary 0 (programmed)  or binary 1 (erased)? 

So, let us discuss the Read operation in FG-MOSFET in the next session, now that we have completed Program and Erase operations.

Till then, "Anyone who is not shocked by the quantum theory has not understood it"   ---- Niels Bohr.

Quiz #1 Switching Activity Calculation for N input gates

This is one of the “many to follow” quizzes and it is taken from Digital Integrated Circuits by Jan M. Rabaey, et al. (One of the best books in the world for learning about the Digital Integrated Circuits). Soon we will have real life circuits(Which are heavily used in the semiconductor industry) to analyze in the quiz section. 

Switching Activity

 We all know that the dynamic power dissipation in is given as :

P(dynamic) = α_0->1C_LV_DD²f

Here the factor α_0->1 is termed as switching activity (or the transition activity). The transition activity is a strong function of logic function (the logic operation being performed by any of the digital gates like AND, OR, NAND, etc). For gates implemented using static CMOS technology, this factor is a multiplication of the two probabilities (The subscript 0->1 is there as for static CMOS gates  power is only consumed when the output switches from 0 to 1 and not other way round as we have a direct path from supply to the output when output transitions from 0 to 1. More to follow on this in the device section):

P₀: The probability that the output will be “0” in present cycle (or for the matter in any cycle)

P₁: The probability that the output will be “1” in the next cycle (or for the matter subsequent cycle of the cycle under consideration).

So α_0->1 = P₀*P₁ or in other words

α_0->1 = P₀*(1-P₀)

If we assume that the inputs to the N input gates are not related to each other (which is a practical consideration) and are distributed uniformly over time, then the switching activity is given as :

α_0->1 = (N₀/2^N)* (N₁/2^N)= N₀(2^N – N₀)/2^2N

N₀: It is the number of “0” entries in the output column of truth table for that gate

N₁: It is the number of “1” entries in the output column of the truth table for the same gate

Now for the problem; suppose we have N input XOR, NOR and NAND gates. Assuming the above assumptions to be valid what should be the switching activity for the above gates? What will be the probability if we replace the N input gates with an inverter?

                                                                   Fig 1. N input NAND Gate

The answers to above questions are simple and easier to find with the above mentioned details.

Feel free to comment and discuss on the same.

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